The present invention relates to a semiconductor memory device, and more particularly to an output enable signal generator of a semiconductor memory device.
Generally, synchronous semiconductor memory devices such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM) input and output data from/to the outside in response to an external clock (CLK_EXT). However, the semiconductor memory devices process data in response to an internal clock. In view of data, it changes the clock which the data is synchronized with. This is called a “domain crossing”.
Several circuits are provided in semiconductor memory devices in order to ensure domain crossing. One of them is an output enable signal generator. The output enable signal generator is a circuit for enabling data transferred in synchronization with an internal clock to be output in synchronization with an external clock (CLK_EXT) after a column address strobe (CAS) latency.
FIG. 1 is a block diagram of a conventional output enable signal generator.
Referring to FIG. 1, the conventional output enable signal generator includes a counter reset signal generating unit 10, an initializing unit 20, a delay locked loop (DLL) clock counting unit 30, a delay model unit 40, an external clock counting unit 50, a latch unit 60, and a comparing unit 70.
The counter reset signal generating unit 10 outputs a first reset signal RST_DLL in response to a reset signal RST and a DLL clock CLK_DLL. The reset signal RST is a signal corresponding to an external command (for example, /RAS, /CAS, /CS, or /WE).
The initializing unit 20 provides an initial count value corresponding to a CAS latency (CL) to the DLL clock counting unit 30 in response to the first reset signal RST_DLL. The following Table 1 shows initial count values and signals S<0:2> output from the initializing unit 20 accordingly when the CAS latency is in the range of 3 to 7.
TABLE 1CLInitial count valueS<2>S<1>S<0>3510144100530116201071001
FIG. 2 is a circuit diagram of the initializing unit 20 of FIG. 1.
Referring to FIG. 2, the initializing unit 20 is enabled in response to the first reset signal RST_DLL to generate signals S<0:2> and R<0:21> for resetting the DLL clock counting unit 30 according to the CAS latency. The CAS latency is a signal output from a mode register set (not shown) and has information on the number of cycles of the external clock CLK_EXT that elapses from the time when a read command (RD, see FIG. 4) in input to the time when data is output.
Referring again to FIG. 1, the DLL clock counting unit 30 counts the DLL clock CLK_DLL from the initial count value to output DLL clock count value CNT_DLL<0:2>. For example, assuming that the initial count value is set to 4 according to the CAS latency, the DLL clock counting unit 30 starts to count the DLL clock CLK_DLL from 4.
The delay model unit 40 stores modeling values of delay components until data is output according to the DLL clock CLK_DLL. A second reset signal RST_CLK is generated by reflecting a modeled delay value on the first reset signal RST_DLL.
The external clock counting unit 50 counts the external clock CLK_EXT in response to the second reset signal RST_CLK, and the latch unit 60 latches the output signals CNT_CLK<0:2> of the external clock counting unit 50 and outputs the external clock count value CNT_RD<0:2> in response to the read command RD.
The comparing unit 70 compares the DLL clock count value CNT_DLL<0:2> to the external clock count value CNT_RD<0:2> and activates the output enable signal OE when the two values are identical to each other.
FIG. 3 is a circuit diagram of the comparing unit 70 of FIG. 1.
Referring to FIG. 3, the comparing unit 70 is configured to compare the 3-bit DLL clock count value CNT_DLL<0:2> to the 3-bit external clock count value CNT_RD<0:2>. The comparing unit 70 outputs the output enable signal OE that is activated when the DLL clock count value CNT_DLL<0:2> is identical to the external clock count value CNT_RD<0:2>. The output enable signal OE is a signal, synchronized with the DLL clock CLK_DLL, that is activated using an initial count value corresponding to a CAS latency in the range from a minimum CAS latency to a maximum CAS latency. For reference, data are output according to the output enable signal OE and burst length information.
FIGS. 4 and 5 are signal timing diagrams illustrating the operation of the output enable signal generator of FIG. 1. Specifically, FIG. 4 illustrates a case where the CAS latency is 4. The operation of the output enable signal generator will be described with FIGS. 1 and 4.
Since the CAS latency is 4, the initial count value of the initializing unit 20 is set to 4, based on Table 1. When the first reset signal RST_DLL becomes logic low, the DLL clock counting unit 30 is responsive to the DLL clock CLK_DLL to output the DLL clock count value CNT_DLL<0:2> that is counted from the initial count value, that is, 4.
Meanwhile, when the second reset signal RST_CLK becomes logic low after the delay time of the delay model unit 40 is reflected on the first reset signal RST_DLL, the external clock counting unit 50 starts to count from zero in response to the external clock CLK_EXT.
At this point, when the read command RD is input, the latch unit 60 latches and outputs 2, which is the count value CNT_CLK<0:2> of the external clock CLK_EXT, as the external clock count value CNT_RD<0:2>. The comparing unit 70 compares the DLL clock count value CNT_DLL<0:2> with the external clock count value CNT_RD<0:2>. When the DLL clock count value CNT_DLL<0:2> is identical to the external clock count value CNT_RD<0:2>, that is, when the DLL clock count value CNT_RD<0:2> becomes 2, the comparing unit 70 activates the output enable signal OE. Data D0, D1, D2 and D3 are output to an external terminal DQ using the output enable signal OE.
FIG. 5 illustrates a case where the CAS latency is 5. The operation of the output enable signal generator will be described with reference to FIGS. 1 and 5.
Since the CAS latency is 5, the initial count value of the initializing unit 20 is set to 3, based on Table 1. When the first reset signal RST_DLL become logic low, the DLL clock counting unit 30 outputs the DLL clock count value CNT_DLL<0:2> that is counted from the initial count value, that is, 3.
Meanwhile, when the second reset signal RST_CLK becomes logic low after the delay time of the delay model unit 40 is reflected on the first reset signal RST_DLL, the external clock counting unit 50 starts to count the external clock CLK_EXT.
At this point, when the read command RD is input, the latch unit 60 latches and outputs 2, which is the count value CNT_CLK<0:2> of the external clock CLK_EXT, as the external clock count value CNT_RD<0:2>. The comparing unit 70 compares the DLL clock count value CNT_DLL<0:2> to the external clock count value CNT_RD<0:2>. When the DLL clock count value CNT_DLL<0:2> is identical to the external clock count value CNT_RD<0:2>, that is, when the DLL clock count value CNT_DLL<0:2> becomes 2, the comparing unit 70 activates the output enable signal OE. Data D0, D1, D2 and D3 are output to an external terminal DQ using the output enable signal OE.
The structure and operation of the conventional output enable signal generator have been described. Hereinafter, the weakness and problems of the conventional output enable signal generator will be described.
First, the CAS latency is a signal output from a mode register set. Thus, the initializing unit 20 has a limitation in that the initial count value is not set until the mode register set is set. In the operation of the semiconductor memory device, the initial count value must be changed by resetting the DLL clock counting unit 30 whenever the CAS latency is changed in a standby state such as a self-refresh operation.
In addition, as the fast circuit operation is required, an external clock CLK_EXT having higher frequency is used and thus the CAS latency is gradually increasing. Therefore, the counting capability of the DLL clock counting unit 30 and the external clock counting unit 50 must be expanded according to the CAS latency. For example, when the DLL clock counting unit 30 and the external clock counting unit 50 are implemented with 3-bit counters, the CAS latency can be ensured up to 7. If the CAS latency is further increased, the capability of the counters constituting the DLL clock counting unit 30 and the external clock counting unit 50 must also be expanded to more than 3 bits. The structure of the counters for the increased bit number causes more current consumption during an active or standby operation.
As the CAS latency increases, the bit number output from the DLL clock counting unit 30 and the external clock counting unit 50 increases. In this case, since the operation time of the comparing unit 70 increases, unwanted additional delay time is needed when generating the output enable signal. Consequently, the output enable signal cannot be generated at a desired time.